Earlier today, the world started to turn around news coming from a fellow website that claimed that ominous TLB-bug stroke Intel’s latest baby, Core i7 series. Transition Lookaside Buffer erratas/bugs are notorious and took financial and reputational tool from Intel and AMD in the past.
Hearing news about TLB bugs happening with Core i7 had the potential to become a story of the year, just like AMD lost huge chunk of market confidence 12 months ago with TLB-bug on Barcelona/Agena (Opteron/Phenom). Could it be that Nehalem architecture has a similar flaw?
Well, prior to running my story, I decided to read the document in question (Intel Core i7 Processor Extreme Edition Series and Intel Core i7 Processor Specification Update November 2008) from one side, and wait until Intel responds from another. While reading the document, it looked to me that the erratas are already fixed, and that the launch platform is actually unaffected by this problem.
Shortly after 10AM PT, I received an answer from Dan Snyder, Intel’s PR manager and CPU specialist. The answer is an official statement from Intel:
This is simply a pointer to a previous document written in April 2007. This document is an application note (advises on programming techniques) that programmers have had since April of 2007. This item in the Nehalem spec sheet is a web pointer, under the heading “spec clarification”. The reporter who wrote this did not contact us and we will try to clarify this with him.
The story was not over here, I also received a detailed clarification over this “issue” that turned into a non-issue:
SPEC CLARIFICATION AAJ1 was initially added due to an issue on the Intel® Core 2 Duo processor which was previously corrected with a BIOS update; this issue does not impact the Nehalem Family of CPUs. There are errata on the Intel® Core i7 processor that relate to the TLB. These all relate to improper translations or error reporting, and all of those that impact functionality have been fixed via BIOS updates prior to Core i7 launch.
As you can read above, mentioned errors was “featured” in initial batch of processors with Conroe architecture (Core 2 Duo). Nehalem itself shipped with bugs (all processors do, that’s why micro-code update feature was implemented in the first place), but not with stability-challenging bug that plagued Core 2 Duo and Quad-Core Phenom/Opteron of yesteryear.
If this error was not solvable other than decreasing performance by castrating L3 cache bandwidth (like Barcelona/Phenom) or a product recall (like Pentium 100), Intel would have one heck of a disaster on their hands. But due to mechanisms implemented by both Intel and AMD (already mentioned micro-code update that is nothing else but a firmware flash for the CPU), small errors and bugs are easily squashed.
A storm in a cup of water, as my grandma would say.